1. Field of the Invention
The present invention relates to an integrated circuit capable of synchronizing multiple outputs, and more particularly, to a source driver of a display device capable of synchronizing multiple outputs.
2. Description of the Prior Art
Liquid crystal display (LCD) devices are used in various devices such as personal computers or television screens due to their advantages of thinness, light weight, and low power consumption. Color liquid crystal display devices with an active matrix system in particular, which are advantageous for controlling image quality with high definition, have become dominant.
FIG. 1 shows a diagram of a prior art liquid crystal display device 10 including an LCD panel 12, a controller 14, a plurality of gate drivers 16, and a plurality of source drivers 20-2n. Though the details of the LCD panel 12 are not illustrated, the LCD panel 12 is constituted from a structure including a semiconductor substrate with transparent pixel electrodes and thin film transistors (TFTs) disposed thereon, an opposing substrate with one transparent electrode formed on an entire surface thereof, and a liquid crystal sealed between these two opposing substrates. Then, by controlling the TFTs, a predetermined voltage is applied to each pixel electrode, and the transmissivity or reflectivity of the liquid crystal is changed by a potential difference between each pixel electrode and the electrode on the opposing substrate. A scanning signal in a pulse form is sequentially transmitted to a scan line on the LCD panel 12 from a corresponding gate driver 16. TFTs connected to the gate line to which a pulse is applied are all turned on. At this point, gray-scale voltages are supplied to the data lines of the LCD panel 12 from the respective source drivers 20-2n and applied to pixel electrodes through the turned-on TFTs. Then, when the TFTs connected to the gate line to which no pulse is applied any longer are turned off, potential differences between the pixel electrodes and the opposing substrate electrode are held for a period until subsequent gray-scale voltages are applied to the pixel electrodes. Then, by sequential pulse application, predetermined gray-scale voltages are applied to all pixel electrodes. By performing gray-scale voltage rewriting in each frame period, an image can be displayed.
FIG. 2 shows a diagram of the source driver 20 of the liquid crystal display device 10 constituting an interface circuit for chip-to-chip data transfer. Since the source drivers 21-2n have the same structure as the source driver 20 shown in FIG. 2, corresponding illustrations and descriptions will be omitted. The source driver 20 includes an RSDS (reduced swing differential signaling) receiver 30, a shift register 40, a data capturing circuit 50, a latch 60, a level shifter 70, a digital-to-analog conversion circuit (which will be hereinafter referred to as a D/A converter) 80, and an output buffer 90. Based on the input signal INV1, the RSDS receiver 30 generates the output signal OUT1 and a data signals DATA to the shift register 40 and the data capturing circuit 50, respectively. The latch 60 holds the data signals captured by the data capturing circuit 50 at the timing of the front edges of the latch signals STB, and then collectively supplies the latched data signals to the level shifter 70 during each horizontal period. The level shifter 70 increases the voltage levels of the data signals DATA from the latch 60, and then outputs the data signals to the D/A converter 80. The D/A converter 80 supplies gray scale voltages corresponding to the logic values of the data signals to the output buffer 90, which then outputs the gray-scale voltages at the timing of the rear edges of the latch signals STB. For the liquid crystal display device 10 to function efficiently, the output signals supplied by the RSDS receivers (referred to as 30-3n in FIG. 3) of the source drivers 21-2n have to be synchronized.
Since the input signals are generated by the controller 14, different input signals encounter different resistance according the distances between the controller 14 and corresponding RSDS receivers. FIG. 3 is a diagram showing an equivalent circuit of the RSDS receiver 30-3n of the source drivers 20-2n. In FIG. 3, VDD and VSS are power sources supplying power to the RSDS receivers 30-3n via a power line PL and a ground line GL, respectively. I1-In are analog current sources. RD1-RDn are parasitic resistors of the power line PL, and RS1-RSn are parasitic resistors of the ground line GL. VD1-VDn and VS1-VSn represent the bias voltages of the RSDS receivers 30-3n, respectively. Usually the RSDS receivers 30-3n are disposed in a way such that the parasitic resistors RD1-RDn and RS1-RSn have the same resistance. The voltage difference established across each parasitic resistor when the liquid crystal display device 10 is operating is represented by Δ. The bias voltages VD1-VDn can be respectively represented by VDD-Δ, VDD-2*Δ, . . . , VDD-n*Δ, and the bias voltages VS1-VSn can be respectively represented by VSS+Δ, VSS+2*Δ, . . . , VSS+n*Δ. Since each RSDS receiver has different bias voltages, the output signals OUT1-OUTn cannot be outputted simultaneously. Therefore, the performance of the prior art liquid crystal display device 10 cannot be optimized.